Rockwell-automation 1772-LP3 PLC - 2/30 Programmable Controller Progra Manuel d'utilisateur

PLC2/30 Programmable ControllerProgramming and Operations Manual

Table of ContentsviiiA.2.3 1/2Slot Addressing A11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.3 System Configurations A16. . .

Timer and Counter InstructionsChapter 552The remaining 4 bits in a word (bits 14-17) are not used to form a BCDnumber. In the accumulated value word,

Timer and Counter InstructionsChapter 553All three timers differ in the way they set and reset status bits, respond torung logic continuity and reset

Timer and Counter InstructionsChapter 554Figure 5.3Timer OnDelay, Timing Diagram for a Preset Value of 9 SecondsONOFFONOFF01234567891011121201204563

Timer and Counter InstructionsChapter 555The Timer Off-Delay instruction (TOF) can be used to turn a device onor off after a timed interval (Figure 5

Timer and Counter InstructionsChapter 556Figure 5.4Timer OffDelay, Timing Diagram for a Preset Value of 9 SecondsONOFFONOFF0123456789101112120120456

Timer and Counter InstructionsChapter 557Figure 5.5Retentive Timer with Retentive Timer Reset Timing DiagramTRUEFALSEONOFF01234567891011121204563789O

Timer and Counter InstructionsChapter 558Unlike the Timer On-Delay instruction, the Retentive Timer instructionretains its accumulated value (Figure

Timer and Counter InstructionsChapter 559 Bit 14 is the overflow/underflow bit. It is set to one when the AC valueof the CTU exceeds 999 or the AC va

Timer and Counter InstructionsChapter 5510timer, the CTU instruction continues to increment its accumulated valueafter the preset value has been reac

Timer and Counter InstructionsChapter 5511The Counter Reset (CTR) instruction is an output instruction that resets theCTU accumulated value and statu

1Chapter 11IntroductionThis manual presents the information you need to program and operateyour Allen-Bradley PLC-2/30 Programmable Controller.After

Timer and Counter InstructionsChapter 5512The Down-Counter (CTD) instruction subtracts one from its AccumulatedValue for each false-to-true transitio

Timer and Counter InstructionsChapter 5513Figure 5.10UpDown Counter Example||00( CTU )110 046PR 220AC 114||02( CTD )110 046PR 220AC 114||03( CTR

Timer and Counter InstructionsChapter 5514An individual timer or counter can time or count up to 999 intervalsor events. By cascading two or more tim

Timer and Counter InstructionsChapter 5515The default word address can be 3, 4 or 5 digits provided the data table issized accordingly. Unlike bit in

Timer and Counter InstructionsChapter 5516Table 5.BTimer InstructionsNOTE: The Timer word address, XXX, is assigned to the timer Accumulated areas of

Timer and Counter InstructionsChapter 5517Table 5.CCounter InstructionsNOTE: The Counter word address, XXX, is assigned to the counter Accumulated ar

Timer and Counter InstructionsChapter 5518one millisecond, whichever is greater, when a data highway interfacemodule is connected to the processor.Th

Timer and Counter InstructionsChapter 5519Figure 5.13Program for Determining Average Scan Time( CTU )050PR 999AC 000( CTU )050PR 999AC 000| / |14( R

Timer and Counter InstructionsChapter 5520Table 5.E contains longer execution times for more complicatedinstructions. Note that all of the Table 5.E

Timer and Counter InstructionsChapter 5521Table 5.DAverage Execution Times for Instructions Described In Chapters 3Through 8 When Instruction is TRUE

IntroductionChapter 112With a user-written program and appropriate I/O modules, the PLC-2/30programmable controller can be used to control many types

Timer and Counter InstructionsChapter 5522Table 5.EAverage Execution Times for WordToFile, Sequencers, Word and BitShifts, File Diagnostic, File Se

Timer and Counter InstructionsChapter 5523As an example, we will calculate the execution time for File-to-File movein the distributed complete mode f

Timer and Counter InstructionsChapter 5524The execution time, T, in microseconds for the complete mode is:T = 99 + 9.8 (Words operated upon per scan)

Chapter 661Data Manipulation InstructionsThe data manipulation instructions are used to transfer or compare datathat is stored in data table words an

Data Manipulation InstructionsChapter 662The Get Byte and Limit Test instructions compare 3-digit values in octalformat using eight bits (one byte) o

Data Manipulation InstructionsChapter 663Figure 6.3Get and Put Instructions||11( PUT )238111 040| G |238130If the word addressed by a Get instructio

Data Manipulation InstructionsChapter 664Figure 6.4Changing a Counter Preset||11( PUT )238111 140||12( CTU )111 040| G |238130PR 238AC 047NOTE: The

Data Manipulation InstructionsChapter 665A Get/Les or Get/Equ pair of instructions forms a single condition forlogic continuity. Alone or with other

Data Manipulation InstructionsChapter 666Figure 6.6GreaterThan Comparison||02()01120 010| G |100030| < |YYY031Reference ValueWhen YYY>100, G

Data Manipulation InstructionsChapter 667Figure 6.8LessThan or EqualTo Comparison||04()03120 010| G |YYY030| < |237040Reference ValueWhen YYY≤

IntroductionChapter 113 Functional Block Instructions- Shift Register instructions- File-to-File and Word-to-File Logic instructions- File-to-File,

Data Manipulation InstructionsChapter 668logic continuity. Condition instructions can be programmed before the GetByte instruction or after the Limit

Data Manipulation InstructionsChapter 669The Get Byte instruction addresses either the upper or lower byte of a datatable word. A 1 is entered after

Data Manipulation InstructionsChapter 6610Table 6.AData Manipulation InstructionsNOTE: Data Manipulation instructions operate upon BCD values and/or

Data Manipulation InstructionsChapter 6611The PLC-2/30 processor can be programmed to perform arithmeticoperations with two BCD values using a set of

Data Manipulation InstructionsChapter 6612Figure 6.12Arithmetic Instruction Word17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00MostSignificantDigitMi

Data Manipulation InstructionsChapter 6613Figure 6.13Add Instruction||11( + )1034111 032| G |520030| G |514031Must be true to allowarithmetic operat

Data Manipulation InstructionsChapter 6614The Multiply instruction tells the processor to multiply the two BCDvalues stored at the Get instruction wo

Data Manipulation InstructionsChapter 6615Figure 6.16Divide Instruction||13( : )000111 067| G |050140| G |025141Must be true to allowarithmetic oper

Data Manipulation InstructionsChapter 6616Table 6.BArithmetic InstructionsNOTE: Arithmetic instructions operate on BCD values in the Data Table. The

Data Manipulation InstructionsChapter 6617If the BCD value is > 4095, the overflow bit (bit 14 of the binary address)will be set on.The binary num

IntroductionChapter 114When using a 1772-SD2 remote I/O scanner/distribution panel, the I/Odevice capacity can be increased from 896 to 1,792 I/O. Th

Data Manipulation InstructionsChapter 6618DATA – The BCD number is 004095 (the largest BCD number that canbe converted to a 12-bit binary number).BIN

Data Manipulation InstructionsChapter 6619BINARYADDR – 125DATA – 111111111111BCDADDR – The BCD number is stored in adjacent data table words 200and 2

Data Manipulation InstructionsChapter 6620Figure 6.20BinarytoBCD Conversion Example RungBINARY TO BCDBINARYADDR: 025DATA: 111111111111BCDADDR: 201-

Chapter 771Output Override and I/O UpdateInstructionsThe user may need programming instructions for certain applicationsrequiring output overrides or

Output Override and I/O Update InstructionsChapter 772Figure 7.1MCR and ZCL Zone Programming|| ( ZCL )||( )||| / || / |( )||||( )||||||||

Output Override and I/O Update InstructionsChapter 773WARNING: MCR or ZCL zones should not be overlapped ornested. Each zone should be separate and c

Output Override and I/O Update InstructionsChapter 774Figure 7.2Scan SequenceI/O ScanPerforms I/OUpdating(Typically0.5ms/128 I/O)Start ofProgramInstr

Output Override and I/O Update InstructionsChapter 775The Immediate Input instruction updates one word of the input image tabledata in advance of the

Output Override and I/O Update InstructionsChapter 776The Immediate Output instruction updates one module group with datafrom one output image table

Output Override and I/O Update InstructionsChapter 777Figure 7.4Immediate Output InstructionReturns toProgramScanModule Group(Output)Immediate Output

IntroductionChapter 115WARNING: Do not use a 1770-T1 or 1770-T2 industrialterminal to edit or change a program or data table valuesin PLC-2/30 memory

Output Override and I/O Update InstructionsChapter 778The Immediate I/O instructions are programmed with the processor inthe program mode. When enter

Output Override and I/O Update InstructionsChapter 779The remote fault zone programming technique is used to disable parts of orthe entire user progr

Output Override and I/O Update InstructionsChapter 7710Figure 7.5Remote I/O Configuration Example0123Module Groups4567Module Groups01Module Groups23M

Output Override and I/O Update InstructionsChapter 7711Fault zones can be programmed around certain parts of the program or theentire program using f

Output Override and I/O Update InstructionsChapter 7712Each fault status bit within a group of four corresponds to two consecutivemodule groups of 32

Output Override and I/O Update InstructionsChapter 7713NOTE: If a fault occurs in a local rack, all racks will behave according totheir last state sw

Output Override and I/O Update InstructionsChapter 7714Figure 7.7Separate Independent Fault Zone Programming for Individual I/OChassis| / |03( MCR )1

Output Override and I/O Update InstructionsChapter 7715Figure 7.8Alternate Independent Fault Zone Programming for Individual I/OChassis| / |03( MCR )

Output Override and I/O Update InstructionsChapter 7716The 1772-SD2 scans remote I/O racks and stores the information in itsbuffer. The processor, du

Output Override and I/O Update InstructionsChapter 7717Table 7.CAverage Execution Times in Microseconds for FILETOFILE AND, OR,XOR Instructions whe

IntroductionChapter 116We use the following terms to describe the various parts of your PLC-2/30system.Chassis — a hardware assembly used to house PC

8Chapter 81Peripheral FunctionsThere are several functions that can be performed with a PLC-2/30 and theindustrial terminal. Some require the use of

Peripheral FunctionsChapter 882Channel C must be on to receive input from a peripheral device. It isinitially on. It can be toggled on/off by pressin

Peripheral FunctionsChapter 883Table 8.CContact Histogram FunctionsFunction Mode Key Sequence DescriptionContact HistogramContinuousRUNRUN/PROGRAMor

Peripheral FunctionsChapter 884The industrial terminal screen can display up to 11 lines of data at onetime. In the continuous mode, the screen will

Peripheral FunctionsChapter 885The cassette load command is accessed by pressing [RECORD] 0 on thePLC-2 family overlay and by pressing either [READ F

Peripheral FunctionsChapter 886During automatic or program verification, the processor will identifydiscrepancies between memory content and the cont

Peripheral FunctionsChapter 887As memory content is being recorded on tape, the industrial terminal willcount the number of user program and data tab

Peripheral FunctionsChapter 888This command is used to verify user program and messages in processormemory with the content in data cartridge tape, o

Peripheral FunctionsChapter 889The data table printout will be followed by the user program in ladderdiagram and block format. The messages will be p

9Chapter 91Report GenerationThe report generation function of the T3 industrial terminal, performed inthe PLC-2 mode, can be used to generate message

2Chapter 21Hardware ConsiderationsThis chapter describes only those hardware items required whenprogramming or operating the PLC-2/30 programmable co

Report GenerationChapter 992 Real-time calendar – you can enter and display the date, and use the datein a message. Date format is month/day/year — J

Report GenerationChapter 993Figure 9.1Alphanumeric Keytop OverlaysAlphanumeric/GraphicKeytop Overlay(1770KAB)AlphanumericKeytop Overlay(1770KAA)The

Report GenerationChapter 994Table 9.AReport Generation CommandsCommand Key Sequence DescriptionEnter Report Generation Function [RECORD] [DISPLAY] Pu

Report GenerationChapter 995the industrial terminal will also display a table (Table 9.B) which showsthe message numbers associated with each message

Report GenerationChapter 996Table 9.CAddress DelimitersDelimiter Format Explanation Message Report Format*XXX* Enter 3digit word addressbetween deli

Report GenerationChapter 997The message print command is self-terminating. [ESC] or [CANCELCOMMAND] can be used to return to ladder diagram display.A

Report GenerationChapter 998The T3 industrial terminal screen size is an 80 x 24 format: 80 columnsacross by 24 lines down. An example message using

Report GenerationChapter 999Table 9.DAlphanumeric/Graphic Keytop DefinitionsKey Function[LINE FEED] Moves the cursor down one line in the same column

Report GenerationChapter 9910Table 9.EIndustrial Terminal Control CodesControl Code Key Sequence Function[CTRL] [P][Column #] [;] [Line #] [A]Positio

Report GenerationChapter 9911Table 9.FASCII Control CodesControl Code1Display2ASCII Mnemonic NameCTRL 03CTRL A3CTRL B3CTRL C3CTRL DCTRL ECTRL FCTRL G

Hardware ConsiderationsChapter 222Figure 2.1PLC2/30 ProcessorDiagnosticIndicatorsKeylock ModeSelect SwitchWhen the memory write protect jumper (Figu

Report GenerationChapter 9912Messages can be printed through program control automatically beenergizing specific message request bits using output la

Report GenerationChapter 9913Messages 1-6 use bits 10-15 of word 027 as message request bits. All othermessages use a user-defined file of message re

Report GenerationChapter 9914Figure 9.5Message Request BitDone Bit Relationship17 10 07 00Message Request Bits Message Done BitsMessageControlWordTh

Report GenerationChapter 9915Figure 9.6Example Program to Request a Message|| ( L )||( U )EventEventDone| / |RequestRequest

Chapter 10101Block TransferBlock transfer is a combination of an instruction and support rungs usedto transfer up to 64 16-bit words of data in one s

Block TransferChapter 10102Figure 10.1Module PositionImage Table Byte RelationshipOutput Image Table17 10 07 00010012017Output ImageTable Word,Lower

Block TransferChapter 10103Figure 10.2Block Transfer DiagramRequest is made inProgram ScanTransfer is madein I/O ScanOutputScanInputScanOnce the modu

Block TransferChapter 10104The format of a block transfer read and a block transfer write instructionwith default values is shown in Figure 10.3.Figu

Block TransferChapter 10105Table 10.BThe First Available Address in Timer/Counter Area of Data Table# I/O Racks First Available Address inTimer/Count

Block TransferChapter 10106The read and write bits are the enable bits for block transfer modules.Either one (or both for a bidirectional transfer) i

Hardware ConsiderationsChapter 223Figure 2.2Memory Write Protect JumperHALFTONE WITH CALLOUTThe remaining words in memory from 4008 to the end of mem

Block TransferChapter 10107Figure 10.4Data Table Locations for a Block Transfer Read InstructionData TableBlock Transfer DataBlock LengthCodeR1R11210

Block TransferChapter 10108During the program scan when input switch 113/02 is closed, theinstruction is enabled and read bit 012/17 is set to 1. In

Block TransferChapter 10109WARNING: When programming multiple writes (or reads) tothe same module, it is possible that a desired transfer will nottak

Block TransferChapter 101010Figure 10.5Programming Multiple Reads from One ModuleBLOCK TRANSFER READDATA ADDR052MODULE ADDR141BLOCK LENGTH04FILE 160

Block TransferChapter 101011When the block transfer instructions are used, the first word andconsecutive words of the timer/counter accumulated area

Block TransferChapter 101012The purpose of block transfer data buffering is to allow the data to bevalidated before it can be used. Data that is read

Block TransferChapter 101013Figure 10.7Buffering Data014140030050130Block LengthCodeR10114R10150152050052 Block Transfer Data (Buffer) Block Transf

Block TransferChapter 1010142. Block Transfer will be enabled during the program scan. The transferwill be performed during an interruption of the ne

Block TransferChapter 101015The data table locations and block instructions for this example are shownin Figure 10.8.

Block TransferChapter 101016Figure 10.8Data Table Locations for Bidirectional Block Transfer013130040070140Block LengthCodeR1111311060070Block Transf

Because of the variety of uses for this equipment and because of thedifferences between this solid state equipment and electromechanicalequipment, the

Hardware ConsiderationsChapter 224modes, program or remote program. (If the keyswitch is inRUN/PROGRAM position, the industrial terminal automaticall

Block TransferChapter 101017The module address is stored in BCD in the data address of the read andwrite instructions. In this example, the module ad

Block TransferChapter 101018The programming of a bidirectional block transfer module depends onwhether the read and write instruction block lengths a

Chapter 11111Jump Instructions andSubroutine ProgrammingThe Jump instruction and subroutine programming allow programmingflexibility and efficiency.

Jump Instructions andSubroutine ProgrammingChapter 11112Figure 11.1JUMP Format|| ( JMP )XXXX = Octal Identification NumberFigure 11.2JUMP to LABEL O

Jump Instructions andSubroutine ProgrammingChapter 11113Instruction overview: Output instruction Can jump 1 or more times to the label with the same

Jump Instructions andSubroutine ProgrammingChapter 11114Table 11.AJump/Subroutine ProgrammingKey Symbol Instruction Name 1770T3 Display Description

Jump Instructions andSubroutine ProgrammingChapter 11115Figure 11.4Multiple JUMPS to LABEL in Subroutine AreaSubroutine Area(1st Subroutine)(2nd Subr

Jump Instructions andSubroutine ProgrammingChapter 11116Figure 11.5Multiple JUMPS to LABEL in Subroutine Area and Multiple Return Pathsto Main Progra

Jump Instructions andSubroutine ProgrammingChapter 11117The Label instruction is always logically true. It should be programmedas the first condition

Jump Instructions andSubroutine ProgrammingChapter 11118enables a subroutine to call itself or loop. This will be explained in Section11.3.3.Instruct

Hardware ConsiderationsChapter 225 PROCESSOR FAULT — Illuminates when the logic circuits controllingthe processor scan fail or if processor error or

Jump Instructions andSubroutine ProgrammingChapter 11119Figure 11.8JUMPTOSUBROUTINE LABEL Operation()016( JSR )06||15( TON )117 200||10()117 01

Jump Instructions andSubroutine ProgrammingChapter 111110The area reserved for subroutines is located in memory between themain program and the messa

Jump Instructions andSubroutine ProgrammingChapter 111111Figure 11.9Representative Subroutine Area()()|| || | / ||| | / |LBLXX( RET )()||LBLXX

Jump Instructions andSubroutine ProgrammingChapter 111112A subroutine can loop or call itself (Figure 11.10b). If this procedureis used, it is recomm

Jump Instructions andSubroutine ProgrammingChapter 111113Figure 11.10(a) Three Levels of Nested Subroutines(b) A Subroutine Can Call Itself or LoopSu

Jump Instructions andSubroutine ProgrammingChapter 111114The Return instruction is an output instruction (Figure 11.11). It is usedonly in the subrou

Chapter 12121Data Transfer File InstructionsThis chapter introduces concepts in two major areas: Files Data monitor modeLater chapters of this manual

Data Transfer File InstructionsChapter 12122Figure 12.1File StructureCounter Addr: 200Starting Address of File: 600File Length - 012 = Preset ValuePo

Data Transfer File InstructionsChapter 12123Figure 12.2File Instruction FormatFILE-TO-FILE MOVECOUNTER ADDR:030POSITION: 001FILE LENGTH: 001FILE A: 1

Data Transfer File InstructionsChapter 12124Externally Indexed CounterWhen the counter is externally indexed, the accumulated value must bepositioned

Hardware ConsiderationsChapter 226When using remote I/O (the 1772-SD2 scanner and the 1771-ASB remoteI/O Adapter), these switches will be set accordi

Data Transfer File InstructionsChapter 12125Figure 12.4Example of an Internally Indexed File InstructionFILE-TO-FILE MOVECOUNTER ADDR: 214POSITION: 0

Data Transfer File InstructionsChapter 12126Figure 12.5Complete Mode OperationData Table14 WordFileOne ScanRate Per Scan = 14 = File Length.Entire fi

Data Transfer File InstructionsChapter 12127Figure 12.6Status Bits for Complete ModeRung ConditionEnable Bit (17)Done Bit (15)Instruction Operation1S

Data Transfer File InstructionsChapter 12128Figure 12.7Distributed Complete Mode OperationData TableScan #1Rates Per Scan = 005File is operated upon

Data Transfer File InstructionsChapter 12129Figure 12.8Status Bits for Distributed Complete ModeRung ConditionEnable Bit (17)Done Bit (15)Instruction

Data Transfer File InstructionsChapter 121210Incremental ModeThe incremental mode allows the file to be operated upon one word perrung transition. Ea

Data Transfer File InstructionsChapter 121211scans equal to the file length. In the incremental mode (r = 0), theoperation must be enabled by a separ

Data Transfer File InstructionsChapter 121212entered. Default values are presented in the instruction block. A charactercursor will indicate where in

Data Transfer File InstructionsChapter 121213Figure 12.11FILETOFILE MOVE OperationMove 10word file (starting at location 410) to10word file (star

Data Transfer File InstructionsChapter 121214WARNING: The counter address for the File-to-File moveinstruction should be reserved for that instructio

Hardware ConsiderationsChapter 227Figure 2.31771 I/O Chassis Backplane Switch Settings for Local I/O SystemsLocalRackNumbersSwitch3541234567OnOnOnOnO

Data Transfer File InstructionsChapter 121215COUNTER ADDR – 200POSITION (set by instruction) – 001FILE LENGTH – 010FILE A – starts at 410 and ends at

Data Transfer File InstructionsChapter 121216Figure 12.14FILETOWORD MOVE OperationCounter 200:PR = 010AC = 005474500505File A(10 words)Words within

Data Transfer File InstructionsChapter 121217Figure 12.15FILETOWORD MOVE FormatFILE-TO-WORD MOVECOUNTER ADDR: 030POSITION: 001FILE LENGTH: 001FILE

Data Transfer File InstructionsChapter 121218Figure 12.16FILETOWORD MOVE Example RungFILE-TO-WORD MOVECOUNTER ADDR: 200POSITION: 005FILE LENGTH: 01

Data Transfer File InstructionsChapter 121219Figure 12.17WORDTOFILE MOVE OperationCounter 050:PR = 010AC = 005474500505File R(10 words)Value in wor

Data Transfer File InstructionsChapter 121220Figure 12.18WORDTOFILE MOVE FormatWORD-TO-FILE MOVECOUNTER ADDR: 030POSITION: 001FILE LENGTH: 001WORD

Data Transfer File InstructionsChapter 121221Figure 12.19WORDTOFILE MOVE Example RungWORD-TO-FILE MOVECOUNTER ADDR: 050POSITION: 05FILE LENGTH: 010

Data Transfer File InstructionsChapter 121222Table 12.BAccessing the Display1Key Sequence Explanation[DISPLAY] X Accesses data monitor format.[DISPLA

Data Transfer File InstructionsChapter 121223Figure 12.20Example Hexadecimal Data Monitor Display of File InstructionFILE-TO-FILE MOVECOUNTER ADDR:03

Data Transfer File InstructionsChapter 121224Data monitor displays, although unique for each File instruction, havecommon characteristics including a

Hardware ConsiderationsChapter 228on the front panel of the local adapter module aid in troubleshooting. Theseindicators are:ACTIVE — Illuminates whe

Data Transfer File InstructionsChapter 121225The command buffer is always displayed when the processor is in programmode. When in run/program mode, t

Data Transfer File InstructionsChapter 121226Digit CursorThe digit cursor initially appears in the left-most position in the commandbuffer. It can be

Data Transfer File InstructionsChapter 121227Table 12.EPaging and Specified PagingKey Sequence Explanation[SHIFT] [↓]Displays the next full page of d

Data Transfer File InstructionsChapter 121228Table 12.FData Entry CommandsKey Sequence Explanation[D] [D] [D] [D]1Data is entered or changed in the C

Chapter 13131Shift Register InstructionsThe file shift instructions are: Shift File Up Shift File Down FIFO Load FIFO UnloadThe first two output in

Shift Register InstructionsChapter 13132The FIFO Load and FIFO Unload output instructions that are always usedtogether to construct an asynchronous w

Shift Register InstructionsChapter 13133input word of data and to shift out one word of data to the output word.The output word data should NOT be co

Shift Register InstructionsChapter 13134Figure 13.3SHIFT FILE UP FormatSHIFT FILE UPCOUNTER ADDR: 030FILE LENGTH: 001FILE: 110-110INPUT ADDR: 010OUTP

Shift Register InstructionsChapter 13135Figure 13.4SHIFT FILE UP Example RungSHIFT FILE UPCOUNTER ADDR: 200FILE LENGTH: 064FILE: 400-477INPUT ADDR: 1

Shift Register InstructionsChapter 13136To program a Shift File Down instruction press keys [SHIFT] [REG] 11.The format that appears and the techniqu

Hardware ConsiderationsChapter 229Three diagnostic indicators are located on the front of the 1771-ASBadapter. These indicators are:ACTIVE — Illumina

Shift Register InstructionsChapter 13137Figure 13.5Format for FIFO LOAD and FIFO UNLOAD InstructionsFIFO UNLOADCOUNTER ADDR:030FIFO SIZE: 001NUMBER I

Shift Register InstructionsChapter 13138WARNING: The counter address specified for FIFO Loadand FIFO Unload instructions should be reserved for these

Shift Register InstructionsChapter 13139Figure 13.6FIFO LOAD and FIFO UNLOAD Example RungFIFO UNLOADCOUNTER ADDR:200FIFO SIZE: 064NUMBER IN FILE: 000

Chapter 14141Bit ShiftsThe Bit Shift instructions are: Bit Shift Left Bit Shift Right Examine Off Shift Bit Examine On Shift Bit Set Shift Bit Reset

Bit ShiftsChapter 14142Figure 14.1BIT SHIFT LEFT/RIGHT Operation3240040116151413121110987654321L17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00L1748

Bit ShiftsChapter 14143Upon false-true transition, bit A from a particular input word will beshifted into the first bit of the bit shift register. Bi

Bit ShiftsChapter 14144Figure 14.2BIT SHIFT LEFT FormatBIT SHIFT SHIFTCOUNTER ADDR: 030NUMBER OF BITS: 001FILE: 110-110INPUT: 010/00OUTPUT: 010/00030

Bit ShiftsChapter 14145Figure 14.3BIT SHIFT LEFT Example RungBIT SHIFT SHIFTCOUNTER ADDR: 200NUMBER OF BITS: 128FILE: 400-407INPUT: 130/17OUTPUT: 420

Bit ShiftsChapter 14146WARNING: The counter address specified for the Bit ShiftRight instruction should be reserved for that instruction. Do notmanip

Bit ShiftsChapter 14147Figure 14.4EXAMINE OFF SHIFT BIT FormatEXAMINE OFFSHIFT BITFILE: 110BIT NO.: 001Numbers shown are default values. Bold number

Hardware ConsiderationsChapter 2210CAUTION: For proper system data communications, alocal/remote system structure with 2 local racks, you must use a1

Bit ShiftsChapter 14148This condition instruction examines a user specified bit in a bit shiftregister, such as shown in Figure 14.1, for an on or 1

Bit ShiftsChapter 14149Figure 14.7EXAMINE ON SHIFT BIT Example RungEXAMINE ONSHIFT BITFILE: 400BIT NO.: 067The Set Shift Bit output instruction sets

Bit ShiftsChapter 141410Figure 14.8SET SHIFT BIT FormatSET SHIFT BITFILE: 110BIT NO.: 001Numbers shown are default values. Bold numbers must be repl

Bit ShiftsChapter 141411Instruction overview: Output instruction 3 words of users program required Key sequence: [SHIFT REG] 17To program a Reset Shi

Chapter 15151Sequencer InstructionsSequencer Instructions are powerful block instructions. They operate onup to 4 words (64 bits) at a time. There ar

Sequencer InstructionsChapter 15152Sequencer instructions, when enabled, increment to the next step and thenthe operation is performed.Figure 15.1Seq

Sequencer InstructionsChapter 15153The Sequencer Output instruction functions in a manner analogous to amechanical drum sequencer.Consider a music bo

Sequencer InstructionsChapter 15154Figure 15.3Sequencer Output Analogy1011110110110100123456StepEquivalentSequencerTableBit LocationsPeg Locations123

Sequencer InstructionsChapter 15155NOTE: When the rung is false, data is not transferred by the instructionand outputs remain in their last state unl

Sequencer InstructionsChapter 15156Figure 15.4Masking Transferred Data0Sequencer Word1 0 1 1 0 1 01Mask Word0 0 1 1 0 0 11Output Word prior toSequenc

Hardware ConsiderationsChapter 2211The 1777-P2 Series C power supply provides 9 amperes to power one ortwo bulletin 1771-I/O chassis. This includes t

Sequencer InstructionsChapter 15157Figure 15.5SEQUENCER OUTPUT FormatSEQUENCER OUTPUTCOUNTER ADDR: 030CURRENT STEP: 000SEQ LENGTH: 001WORDS PER STEP:

Sequencer InstructionsChapter 15158Figure 15.6SEQUENCER OUTPUT Example RungSEQUENCER OUTPUTCOUNTER ADDR: 054CURRENT STEP: 007SEQ LENGTH: 009WORDS PER

Sequencer InstructionsChapter 15159the data monitor display of a sequencer instruction and a file instructionshould be noted. The Sequencer Output in

Sequencer InstructionsChapter 151510The Sequencer Input instruction is a rung-conditioning instruction. Itcompares machine input and other input data

Sequencer InstructionsChapter 151511WARNING: The counter address for the Sequencer Inputinstruction should be reserved for the instruction and theins

Sequencer InstructionsChapter 151512An example rung containing the Sequence Input instruction is shownin Figure 15.10. The following parameters have

Sequencer InstructionsChapter 151513The Sequencer Load instruction is an output instruction. It is used to loaddata into table locations such as file

Sequencer InstructionsChapter 151514 Output Instruction Key sequence [SEQ] 2 Order of operation is increment then load Counter is indexed by the inst

Sequencer InstructionsChapter 151515Figure 15.11SEQUENCER LOAD FormatSEQUENCER LOADCOUNTER ADDR: 030CURRENT STEP: 000SEQ LENGTH: 001WORDS PER STEP: 1

Sequencer InstructionsChapter 151516Figure 15.12SEQUENCER LOAD Example RungSEQUENCER LOADCOUNTER ADDR:0056CURRENT STEP:008SEQ LENGTH:012WORDS PER STE

Chapter 331Data TableThis chapter introduces concepts and terminology necessary for a generalunderstanding of programmable controller memory. It expl

Chapter 16161File Logic InstructionsThis section assumes the reader has Chapter 12, Data Transfer FileInstructions, and is familiar with the concepts

File Logic InstructionsChapter 16162This output instruction operates on the contents of two data files A and Band places the result of the operation

File Logic InstructionsChapter 16163Figure 16.2FILETOFILE AND FormatFILE TO FILE ANDCOUNTER ADDR: 030POSITION: 001FILE LENGTH: 001FILE A: 110-110FI

File Logic InstructionsChapter 16164Figure 16.3FILETOFILE AND Example RungFILE TO FILE ANDCOUNTER ADDR: 050POSITION: 001FILE LENGTH: 006FILE A: 410

File Logic InstructionsChapter 16165Programming of FiletoFile OR InstructionWARNING: The counter address for the File-to-File ORinstruction should

File Logic InstructionsChapter 16166Instruction Overview: Output instruction Key Sequence [FILE] 18 Requires six words of user program Can operate in

File Logic InstructionsChapter 16167Programming File Complement InstructionWARNING: The counter address for the File-to-FileComplement instruction sh

File Logic InstructionsChapter 16168Figure 16.5 shows the format of Figure 16.4 after values for the followingcondition have been entered:COUNTER ADD

File Logic InstructionsChapter 16169Figure 16.6WORDTOFILE LOGIC OperationsOperationAND, OR, XOR123456File B123456File RIn this diagram, a logic ope

File Logic InstructionsChapter 161610 Counter is not modified by instruction. Needs to be externally indexedby user program.Programming WordtoFile

Data TableChapter 332A group of 16 bits makes up a word. This word can be thought of as beingmade up of two 8-bit bytes; a lower byte and an upper by

File Logic InstructionsChapter 161611Figure 16.8 shows the format of Figure 16.7 after data has been entered forthe following conditions:COUNTER ADDR

File Logic InstructionsChapter 161612Table 16.ETruth Table for Logical WORDTOFILE ORCorresponding Bit InBit In Word File BFile R110010101110Instruc

File Logic InstructionsChapter 161613(Figure 16.6). If the bits are both 1 or 0, a 0 is stored in the correspondingbit of File R. For other condition

Chapter 17171File Search and File DiagnosticInstructionsThe File Search instruction locates all words in a file whose data isidentical to a specific

File Search and File Diagnostic InstructionsChapter 17172The process continues until the end of the file is reached (position = filelength), at which

File Search and File Diagnostic InstructionsChapter 17173Figure 17.2FILE SEARCH FormatFILE SEARCHCOUNTER ADDR: 030POSITION: 000FILE LENGTH: 001WORD A

File Search and File Diagnostic InstructionsChapter 17174Figure 17.3FILE SEARCH Example RungFILE SEARCHCOUNTER ADDR: 200POSITION: 003FILE LENGTH: 064

File Search and File Diagnostic InstructionsChapter 17175Figure 17.4FILE DIAGNOSTIC012017File AXOR310315File B320325File RXOR Instruction SetUp(A.)R

File Search and File Diagnostic InstructionsChapter 17176Programming File Diagnostic InstructionWARNING: The counter address specified for the FileDi

File Search and File Diagnostic InstructionsChapter 17177COUNTER ADDR – 200FILE LENGTH – 006FILE – First word is 320, last word is 325BASE – First wo

Introduction 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 Introduction to This Manual 11. . . . . . . . . . . .

Data TableChapter 333Figure 3.2PLC2/30 Memory Organization (Expanded Data Table)User Program Storage(User Program BeginsAfter End of LastData Table

Chapter 18181Troubleshooting AidsThe following troubleshooting aids are useful during starting-up and whentroubleshooting a system: Bit manipulation

Troubleshooting AidsChapter 18182Function DescriptionKey SequenceModeRemoving a FORCE OFF Test or Run/Program [FORCE OFF] [REMOVE] Position the curso

Troubleshooting AidsChapter 18183Bit monitor can function when the processor is in any mode. By pressingthe key sequence [SEARCH] 53 [Key Sequence of

Troubleshooting AidsChapter 18184All force on or all force off functions can be removed at once in ladderdiagram display by breaking communications b

Troubleshooting AidsChapter 18185The Temporary End instruction can be used to test or debug a program upto the point where it is inserted. It acts as

Troubleshooting AidsChapter 18186Section 1.2.3, Industrial Terminal Compatibility.) Those ERR messages donot contain the 4-digit hex value and do not

Chapter 19191Special Programming TechniquesThere are several programming techniques that offer versatile control ofthe process of machine operation.

Special Programming TechniquesChapter 19192When bit 112/04 makes a false-true transition, the scan counter begins toincrement once each scan. When th

AppendixAA1AddressingAfter reading this appendix you should be able to understand: the various addressing modes that you can use with your processors

AddressingAppendix AA2Figure A.1Hardware/Data Table Addressing RelationshipsConcept ExampleHardware Terminology Hardware TerminologyInput (1) or Outp

Data TableChapter 334The first 128 words of the memory are set aside for data table storage.This number includes 32 words for I/O image tables (i.e.,

AddressingAppendix AA3The processor addresses two I/O module slots as one I/O group.Each physical 2-slot I/O group is represented by a word in the in

AddressingAppendix AA4Figure A.2Illustration of 2slot Addressing with Two 8point Input Modules17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00NOTE:

AddressingAppendix AA5Using 8Point I/O ModulesFigure A.3Illustration of 2slot Addressing with 8point Input and Output Modules17 16 15 14 13 12 11

AddressingAppendix AA6Using 16Point I/O ModulesHigh-Density (16-point) I/O modules provide 16 input terminals or 16output terminals. 16-point I/O m

AddressingAppendix AA7that performs the opposite (complementary) function; an input modulecomplements an output module and vice-versa.You can use an

AddressingAppendix AA8The processor (by way of the adapter) addresses one I/O module slot asone I/O group.Each 1-slot I/O group is represented by a w

AddressingAppendix AA9Figure A.6Illustration of 1slot Addressing with 16point I/O Modules0001020304050607101112131415161700010203040506071011121314

AddressingAppendix AA10Figure A.7Assigning I/O Rack Numbers with 1slot AddressingAssignedI/O rack number 1AssignedI/O rack number 2I/O Group No.01 2

AddressingAppendix AA11Figure A.8Example of 1slot AddressingRack 1 Rack 2I/O Group No.01 23 45 67 01 23 45 67I/O Group 1Address1 1 1I/O Group 1Addre

AddressingAppendix AA12You select 1/2-slot addressing by setting two switches in the I/O chassisbackplane switch assembly. See your scanner’s or adap

Data TableChapter 335These memory locations cannot be accessed by the user. Their wordaddresses are not available for addressing of any kind. The pro

AddressingAppendix AA13Figure A.9Illustration of 1/3slot Addressing Using a 32point I/O Module0632-point Input Module1/2-slotI/O Group01/2-slotI/O

AddressingAppendix AA14Assigning I/O Rack NumbersWhen you select 1/2-slot addressing, each slot corresponds to two I/Ogroups. You still assign one ra

AddressingAppendix AA15Figure A.11 illustrates addressing 4 modules, each with the same I/O groupnumber, but in four different racks of a single I/O

AddressingAppendix AA164/5, etc.) or they will not work. (Some two-slot B.T. modules use the lowerslave bus on the I/O chassis backplane for intramod

AddressingAppendix AA17Table A.ASeries B, 1771 Universal I/O Chassis, Addressing Modes vs. I/O AdaptersAddressing ModeI/O Adapter Cat. No. I/O Points

AppendixBB1Number SystemsThere are four numbering systems used with programmable controllers.They are: Decimal Octal Binary HexadecimalThese numberin

Number SystemsAppendix BB2The octal numbering system is used to address word and bit locations inthe data table. Its number set is composed of eight

Number SystemsAppendix BB3The binary numbering system uses a number set that consists of twodigits: the numbers 0 and 1. All information in memory is

Number SystemsAppendix BB4Binary coded decimal (BCD) uses an arrangement of 12 binary digits torepresent a 3-digit decimal number from 000 to 999 (Fi

Number SystemsAppendix BB5Table B.ABCD RepresentationPlace Value23 (8) 22 (4) 21 (2) 20 (1)Decimal Equivalent0000000011000011110000110011000101010101

Data TableChapter 336CAUTION: Word 027 is reserved for processor use. Do not putblock transfer or output modules in rack 2, I/O group 7.Timer/Counter

Number SystemsAppendix BB6Table B.BOctal RepresentationPlace Value22 (4) 21 (2) 20 (1)Octal Equivalent00001111001100110101010101234567The hexadecimal

Number SystemsAppendix BB7Figure B.6HexadecimaltoDecimal Conversion0 x 163 = 01 x 162 = 25610 x 161 = 1607 x 160 = 701A701A716 = 42310225616074231

AppendixCC1Programming .01Second TimersThe bulletin 1772 Mini-PLC-2 Programmable Controller permits you toenter On Delay Timer (TON), Off Delay Time

Programming .01Second TimersAppendix CC2Given any preset value, a Mini-PLC-2 controller timer is accurate to withinone interval of its time base (an

Programming .01Second TimersAppendix CC3Figure C.1Timing Diagram101010InternalClockPulsesEnabledBit 17TimedBit 15Begin TimingT = 3 2 < T < 3On

Programming .01Second TimersAppendix CC4In general, 10-msec timers are used for these functions: monitor events on a high-speed assembly or transfe

Programming .01Second TimersAppendix CC5Changing the timer presets in this manner also enables you to fine-tune thesystem without physically adjusti

Programming .01Second TimersAppendix CC6The Mini-PLC-2 Processor performs an I/O scan and then a program scan,in sequence. Scan time is the sum of t

Programming .01Second TimersAppendix CC7The processor can also update a timer only at the instant it is executingthat timer instruction. Remember th

Programming .01Second TimersAppendix CC8Figure C.2Typical Timing Diagram for 0.01Second Timer89 msec.89 msec.89msec.Start of program scanSame 0.

Data TableChapter 337CAUTION: If a remote I/O configuration is being used, words1258 and 1268 may be used to store remote I/O fault bits. If thisis t

Programming .01Second TimersAppendix CC9Figure C.3Typical 0.01Second Timer Programming()01405|| ()03015 01410|| ()03015 01404( IOT )014234||1

Programming .01Second TimersAppendix CC10Assume the processor is using a 128-word data table and has 1,024 wordsof memory. If all memory words are u

Numbers1slot addressing, A81/2slot addressing, A1110msec timersprogramming techniques, C5typical applications, C41771P2 auxiliary powe

IndexI–2dependent programming, 712digital cassette recorder, 84displaying and locating errors, 86divide instruction, 614downcounter inst

IndexI–3ladder diagram logic, 42last state switch, 26leading edge oneshot, 191les and equ instructions, 64loading memory from a data car

IndexI–4shift file down instruction, 135shift file up instruction, 133special techniques, 191timer and counter instructions, 514wordtof

With offices in major cities worldwideWORLDHEADQUARTERSAllen-Bradley1201 South Second StreetMilwaukee, WI 53204 USATel: (414) 382-2000Telex: 43 11 016

Data TableChapter 338Figure 3.3PLC2/30 Memory Organization (Default Configuration)Processor Work AreaNo. 1Processor Work AreaNo. 2Timer/CounterAccum

Data TableChapter 339Each bit in the input image table may have a corresponding real hardwareterminal on the I/O rack associated with it, although th

Data TableChapter 3310Figure 3.4Relation of Word Address to Hardware17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00OutputImageWordUnassigned: Availab

Data TableChapter 3311Timer/Counter Preset Values, Bit/Word StorageThis area of memory is used to store preset values of timer/counterinstructions. T

Data TableChapter 3312Table 3.AData Table ConfigurationFunction Mode Key Sequence DescriptionData Table Configuration ProgramProgram[SEARCH][5][0][Nu

Table of Contentsii3.3.2 Instruction Address 318. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Fundamental Operation 321. . .

Data TableChapter 3313After you have determined the layout of the data table, press [SEARCH][5] [0]. The following display appears:NUMBER OF 128-WORD

Data TableChapter 3314After the number of I/O racks is selected, the industrial terminal willcompute and enter the data table size.Anytime you reduce

Data TableChapter 3315additional 7 timer/counter instructions become available. The previousoutput image table addresses 0208-0268 are now reserved f

Data TableChapter 3316You program is a group of ladder diagram instructions used to control anapplication. It is initially entered into memory using

Data TableChapter 3317The message storage area begins after the END of user program statementand it stores the alphanumeric characters of the message

Data TableChapter 3318If a bit is off (0), its corresponding output device is off (de-energized).Output image table bits are controlled by user progr

Data TableChapter 3319Figure 3.5Instruction Address TerminologyConcept ExampleHardware Terminology Hardware TerminologyInput (1) or Output (0)Rack No

Data TableChapter 3320Figure 3.6Bit Address to Hardware Relationship (2slot Addressing)17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00BitTerminalOut

Data TableChapter 3321The hardware-program interface is illustrated in Figure 3.7 by showingthe operational relationship between the input and output

Data TableChapter 3322Figure 3.7Relationship of Word Address to Hardware17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00100101111110000100012810001011

Table of Contents iii5.4 Programming Timer and Counter Instructions 514. . . . . . . . . . . . . 5.5 Scan Time and Instruction Execution Times 5

Data TableChapter 3323As you program your application, you should carefully record thedata table addresses of the program elements. The importance of

Data TableChapter 3324Figure 3.8Example of Data Table Word MapFROM (32 WORDS) TOWORDADDRESSWORDADDRESS000040100140200240037077137177237277300Out-puts

Data TableChapter 3325Figure 3.9Example of Data Table Map0001363740414243444546475051DESCRIPTIONBIT NUMBER17 1007 00STARTING WORD ADDRESS000110101101

Data TableChapter 3326Figure 3.10Example of Data Table Word Assignments01256701456WORD ADDRDESCRIPTIONWORD ADDRDESCRIPTION20 Master cycle time, ACDri

Data TableChapter 3327This form can be used for any one of the three Sequencer instructions tolog the data associated with each step.This information

Data TableChapter 3328Figure 3.12Example of Sequencer Table Bit AssignmentsSEQUENCERCOUNTER ADDR: FILE to SEQ LENGTHWORD ADDR:MASK ADDR:MASKSTEP

Data TableChapter 3329placement can be found in the PLC-2/20, PLC-2/30 ProgrammableController Assembly and Installation Manual (publication no. 1772-

Data TableChapter 3330 Output image table words can be used for storage when thecorresponding input image table words are used for nonblock transfer

Data TableChapter 3331ALLEN-BRADLEYConnection Diagram AddressingBULLETIN 1771 I/O ChassisPROJECT NAMEPAGEDATEDESIGNEROF(8-point Modules)

Data TableChapter 3332Bulletin 1771 I/O ChassisCONNECTION DIAGRAM ADDRESSING WORKSHEET(16-point Modules)PROJECT NAMEPAGEDATEDESIGNEROF

Table of Contentsiv7.4.2 Independent Programming 713. . . . . . . . . . . . . . . . . . . . . . . . . 7.5 I/O Update Times 715. . . . . . . . .

Data TableChapter 3333ALLEN-BRADLEYProgrammable ControllerDATA TABLE WORD MAP(1024 WORD)PROJECT NAMEPROCESSORDATA TABLE SIZEPAGE OFDESIGNERFROM(32 WO

Data TableChapter 3334ALLEN-BRADLEYProgrammable ControllerDATA TABLE WORD MAP(128 WORD)PROJECT NAMEPROCESSORDATA TABLE SIZEPAGE OFDESIGNERSTARTING WO

Data TableChapter 3335CommentsALLEN-BRADLEYProgrammable ControllerDATA TABLE WORD ASSIGNMENTS(64 WORD)PROJECT NAMEPROCESSORDATA TABLE SIZEDESIGNER012

Data TableChapter 3336PROJECT NAMEPROCESSORDATA TABLE SIZEDESIGNER00000000111111110123456701234567000000001111111101234567012345670000000011111111012

Data TableChapter 3337PROJECT NAMEPROCESSORDATA TABLE SIZEDESIGNERALLEN-BRADLEYProgrammable ControllerSEQUENCER TABLE BIT ASSIGNMENTSPAGE OFSEQUENCER

Chapter 441Introduction to ProgrammingThe user’s program is a group of ladder diagram and functional blockinstructions used to control an application

Introduction to ProgrammingChapter 442Programmable controller ladder diagram logic closely resembles hardwiredrelay logic. Hardwired relay control sy

Introduction to ProgrammingChapter 443Programmable controllers have many of the capabilities of hardwired relaycontrol systems. Control functions sim

Introduction to ProgrammingChapter 444The condition of the Examine On instruction is either true or false: True – the addressed memory bit is one, me

Introduction to ProgrammingChapter 445Figure 4.5Examine Off Instruction| / |05()14112 012The output instructions set an addressed memory bit to one

Table of Contents v10.2.2 Block Length 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 File Address 105. . . . . .

Introduction to ProgrammingChapter 446CAUTION: The Output Energize instruction can beprogrammed unconditionally for some types of specializedprogramm

Introduction to ProgrammingChapter 447by an Output Unlatch instruction. If power is lost and back-up battery forCMOS RAM memory is maintained, all la

Introduction to ProgrammingChapter 448When the Mode Select Switch is changed from the RUN or RUN/PROGposition, the last true Output Latch or Output U

Introduction to ProgrammingChapter 449The branch instructions allow more than one combination of inputconditions to energize an output device (Figure

Introduction to ProgrammingChapter 4410Figure 4.12Nested Branching vs. Equivalent Logic|| ()A||B||D||||E||C|| ()A||B||D||||E||C||CBran

Introduction to ProgrammingChapter 4411Figure 4.13Example Original Rung With First Part of Duplicate Rung||00()00110 010||00110||01110||01110| /

Introduction to ProgrammingChapter 4412This procedure allows the processor to make a smooth transition fromone form of the rung to the other form dur

Introduction to ProgrammingChapter 4413WARNING: Use only Allen-Bradley authorized programmingdevices to program Allen-Bradley programmable controller

Introduction to ProgrammingChapter 4414Table 4.ARelayType InstructionsNOTE: Examine and Output addresses, XXX/XX, can be assigned to any location in

Introduction to ProgrammingChapter 4415The ladder diagram instructions are entered with the processor in theprogram mode. When entered, they are disp

Table of Contentsvi12.5.1 Accessing the Data Monitor Mode 1221. . . . . . . . . . . . . . . . . . . 12.5.2 Data Monitor Display 1224. . . . . . .

Introduction to ProgrammingChapter 4416Table 4.BHelp DirectoriesFunction Mode Key Sequence DescriptionHelp Directory Any [HELP] Displays a list of th

Introduction to ProgrammingChapter 4417entered is the word address for the Output instructions. The industrialterminal will locate all uses of the wo

Introduction to ProgrammingChapter 4418If found, the rung containing the first occurrence of the address and/orinstruction will be displayed as well

Introduction to ProgrammingChapter 4419The cursor will go directly to the first rung from anywhere in user programby pressing the [SEARCH][↑] keys.Wh

Introduction to ProgrammingChapter 4420Table 4.DEditing Functions1Function Mode Key Sequence DescriptionInserting a ConditionInstructionProgram [INSE

Introduction to ProgrammingChapter 4421the instruction will be inserted before the END statement or subroutinearea.The other way to insert an instruc

Introduction to ProgrammingChapter 4422unlatch instructions are cleared to zero. All other word and bit addressesare not cleared when a rung is remov

Introduction to ProgrammingChapter 4423WARNING: When the address of an instruction whose datais to be changed duplicates the address of other instruc

Introduction to ProgrammingChapter 44242. Block Transfer Read and Write instructions, Jump, Jump toSubroutine, MCR, ZCL and Temp End instructions can

Introduction to ProgrammingChapter 4425WARNING: When the address of a new instruction duplicatesthe address of other instructions in the program, the

Table of Contents vii15.3.1 Operation of the Sequencer Load Instruction 1513. . . . . . . . . . . 15.3.2 Instruction Overview 1514. . . . . . .

Introduction to ProgrammingChapter 4426 [RECORD] key is used to enter a change into user program. Oncepressed, the changed program is active immediat

Introduction to ProgrammingChapter 4427Step 1 – Press [DISPLAY] 0 or 1 for data monitor mode.Step 2 – Press [SEARCH] 51 for on-line data change.Step

Introduction to ProgrammingChapter 4428CAUTION: If the rung logic is true, the output instruction willbe enabled immediately. Before pressing the [RE

Introduction to ProgrammingChapter 4429data has been entered using the data monitor mode. See Insert anInstruction, above.WARNING: When the [RECORD]

Introduction to ProgrammingChapter 4430The rung will become active immediately.Programming InterruptionsIf communication between the industrial termi

Introduction to ProgrammingChapter 4431Table 4.EClear Memory Functions1Function Mode Key Sequence DescriptionData Table Clear Program [CLEAR MEMORY]

Introduction to ProgrammingChapter 4432Total Memory ClearThe complete memory can be cleared by positioning the cursor on the firstinstruction of the

Introduction to ProgrammingChapter 4433Figure 4.16Storage Bit Example|| ()1|| ()||2||8||3||9||4||10||5||11||6||12||7||13|| ()1||2|

Introduction to ProgrammingChapter 4434 One series condition instruction can be used with a Sequencer Inputand an Examine On or Off Shift Bit in ser

Chapter 551Timer and Counter InstructionsTimer and Counter instructions are output instructions internal to theprocessor. They provide many of the ca